Conductor Clearance: Via Hole Tab

The contents of the Via hole sub-tab in the Conductor Clearance tab of the Rule Editor dialog are described below. This sub-tab allows you to optionally specify minimum clearances for via holes. This is done by specifying a value in the cell where the Clearance type row intersects with a column that represents the relevant net and layer configuration.

Item		Description
Clearance Priority		Allows you to select how the effective value for conductor clearance is set. This can be set by searching a hierarchical list of clearance values. Clearance rules that are set in the Conductor Clearance: Voltage Difference Tab, Constraint Browser or the Default Design Rule Stack section in Rule Editor are followed, in the hierarchical order shown below. Alternatively, you can specify that the largest clearance value is used that is set in either Constraint Browser or Rule Editor.
	Use hierarchy	The effective value for conductor clearance is set by checking clearance rules in the following order. The first clearance value that is found is used. Click the rows in the following image for a description of where the relevant values are set. Note Item 1: if a voltage is set against a Net, then clearances are checked using the difference between the voltages of the nets. This is defined in the Voltage difference clearance table, in the Conductor Clearance: Voltage Difference Tab in Rule Editor. If Nets do not have a voltage defined, then the voltage difference is set in the Default Attributes for Signal section. Item 2: clearance values are used that are set in the Rule Area Attributes dialog for the Net. Items 3 to 8: if a voltage is set against a Net and a table stack is also set against a Net in the Design Rule tab in Constraint Browser, then the specified table stack is used as the clearance. Item 9: if no voltage or clearance stack is set for a Net, then the Default design rule stack determines the clearances.
	Use largest value	The largest clearance value is used that is set in either the Design Rule sub-tab, Voltage Difference Clearance section in Constraint Browser, or in the Default design rule stack section in Rule Editor. In the following example, a clearance of 0.1 mm is set in the Default design rule stack, and a clearance formula of 0.00305 * Vdiff + 0.05000 is specified in the Clearance dialog. Below approximately 16V, the clearance is defined by the Default design rule stack. Above this voltage, the clearance is defined by the formula as this produces the largest clearance values.

Clearance Type Settings

Clearances between types of via hole are described below. Clearances for build-up via holes can be specified for via holes in the same net, or in different nets. They can also be specified on the same layer, or on different layers.

Clearance Type	Net Type	Layer Type	Description
Build-up via hole - Build-up via hole	Other net	Same Layer	The clearance between holes in build-up vias in other nets, but on the same layer.
		Other Layer	The clearance between holes in build-up vias in other nets and on different layers.
	Same net	Same Layer	The clearance between holes in build-up vias in the same net and on the same layer.
		Other Layer	The clearance between holes in build-up vias in the same net, but on different layers.
Build-up via hole - Other via holes	Other net	Same Layer	For a hole in a build-up via, and a hole in a via other than a build-up via, this is the clearance between holes in another net, but on the same layer.
		Other Layer	For a hole in a build-up via, and a hole in a via other than a build-up via, this is the clearance between holes in other nets, on different layers.
	Same net	Same Layer	For a hole in a build-up via, and a hole in a via other than a build-up via, this is the clearance between holes in the same net and the same layer.
		Other Layer	For a hole in a build-up via, and a hole in a via other than a build-up via, this is the clearance between holes in the same net, but on different layers.
Other via holes - Other via holes	-	-	The clearance between holes in vias other than build-up vias.