Task 6: Defining Skew Groups

In this topic, you will define and constrain the Skew Groups that are required for this design.

1. Using the MyHSDesign1.pdes design from the previous topic, launch Constraint Browser from the Home tab on the ribbon.
2. In Constraint Browser, click Select All in the Signals tab to select all the signals.
3. In Constraint Browser, click Create Skew Group on the ribbon or click Edit > Create Skew Group on the menu. The Create Skew Group dialog is launched.

Figure 1: Create Skew Group Dialog

4. In the 1: Select Signals section, select signals LPDDR2_CA[0-9] by dragging the cursor over the LPDDR2_CA[ ] signals to select them.
5. Select the clock differential pair LPDDR2_CLK_C - LPDDR2_CLK_T by pressing Ctrl, and then clicking it. Components should now be displayed in the other fields in the dialog.

Figure 2: Create Skew Group Dialog

6. In the 2: Select Drivers section, ensure that component U1 is selected.
7. In the 3: Select Receivers section, ensure that component U2 is selected.
8. In the 4: Select Base Signal section, select the Base column to specify the differential pair clock as the base signal.

Figure 3: Create Skew Group Dialog

9. In the 5: Skew Group Name section, define the name of the Skew Group as “CLK_TO_ADDRESS_U1-U2” and click Create. It is added to the Skew Groups section, on the right side of dialog.

Figure 4: Create Skew Group Dialog

10. Using the above procedure, create the following skew groups.

1. Select Signals	2. Select Drivers	3. Select Receivers	4. Select Base Signal	5. Skew Group Name
LPDDR2_CA [0-9] LPDDR2_CLK_C - LPDDR2_CLK_T	U1	U3	LPDDR2_CLK_C-LPDDR2_CLK_T (Differential Pair)	CLK_TO_ADDRESS_U1-U3
LPDDR2_DQ [0 - 7] LPDDR2_DQ0S_C - LPDDR2_DQ0S_T	U1	U2	LPDDR2_DQ0S_C-LPDDR2_DQ0S_T (Differential Pair)	ByteLane0
LPDDR2_DQU1 [8-15] LPDDR2_DQ1S_C-LPDDR2_DQ1S_T	U1	U2	LPDDR2_DQ0S_C-LPDDR2_DQ0S_T (Differential Pair)	ByteLane1
LPDDR2_DQ [16-23] LPDDR2_DQ2S_C- LPDDR2_DQ2S_T	U1	U2	LPDDR2_DQ0S_C-LPDDR2_DQ0S_T (Differential Pair)	ByteLane2
LPDDR2_DQ [24-31] LPDDR2_DQ3S_C- LPDDR2_DQ3S_T	U1	U2	LPDDR2_DQ0S_C-LPDDR2_DQ0S_T (Differential Pair)	Bytelane3
LPDR2_DQ [32-39] LPDDR2_DQ4S_C- LPDDR2_DQ4S_T	U1	U2	LPDDR2_DQ0S_C-LPDDR2_DQ0S_T (Differential Pair)	Bytelane4
LPDDR2_DQ [40-47] LPDDR2_DQ5S_C- LPDDR2_DQ5S_T	U1	U2	LPDDR2_DQ0S_C-LPDDR2_DQ0S_T (Differential Pair)	Bytelane5
LPDDR2_DQ [48-55] LPDDR2_DQ6S_C- LPDDR2_DQ6S_T	U1	U2	LPDDR2_DQ0S_C-LPDDR2_DQ0S_T (Differential Pair)	Bytelane6
LPDDR2_DQ [56-63] LPDDR2_DQ7S_C- LPDDR2_DQ7S_T	U1	U2	LPDDR2_DQ0S_C-LPDDR2_DQ0S_T (Differential Pair)	Bytelane7
LPDDR2_DQ0S_C- LPDDR2_DQ0S_T LPDDR2_DQ1S_C- LPDDR2_DQ1S_T LPDDR2_DQ2S_C- LPDDR2_DQ2S_T LPDDR2_DQ3S_C- LPDDR2_DQ3S_T LPDDR2_DQ4S_C- LPDDR2_DQ4S_T LPDDR2_DQ5S_C- LPDDR2_DQ5S_T LPDDR2_DQ6S_C- LPDDR2_DQ6S_T LPDDR2_DQ7S_C- LPDDR2_DQ7S_T LPDDR2_CLK_C-LPDDR2_CLK_T	U1	U2	LPDDR2_DQ0S_C-LPDDR2_DQ0S_T (Differential Pair)	DQS_TO_CLK

11. Save the design, and close the Create Skew Group dialog.

The above procedures are demonstrated in the following video.