Task 14: Adding Vias to a Design

Using the Padstack command, it is possible to add vias into a design and connect them to flooded areas. In this task, you will set up a via size and span, and make connections to flooded planes.

  1. On the Padstack tab, click Padstack. The Padstack dialog is displayed.
  2. Set the active layer to Conductor-1.
  3. Set the parameters shown below.

Figure 1: Padstack Settings

Note
From the Padstack name pull down list, select the larger-sized via "v80h50m60" to add larger padstacks where larger space is available.
  1. Frame view the area below IC4, the 65 pin device.
  2. On the status bar, click   Layer Settings to display the Layer Settings panel.
  3. In the Layer Settings panel, ensure that only the Conductor-1 and Conductor-4 layers are visible by selecting the Visible layer check box for just these layers.
  4. With the via attached to the cursor, move over the flooded area and then right-click and select Specify Net on the assist menu.
  5. Click the GND0V flooded area. GND0V is now shown next to the via attached to the cursor.
  6. Click to place the via.

Figure 2: Adding a Via

  1. Repeat as necessary to place vias near to GND0V pins on components.
  2. Select the larger of the vias from the Padstack name box.
  3. Frame the area showing both the topside VIN_12V flooded areas, shown below.

Figure 3: Via Pattern

  1. Add the larger vias to the flooded areas as shown.

To complete your design, a polygon area fill needs to be added on Conductor-3. This connects the two VIN_12V flooded areas. Do this by following the instructions in Task 12.

Figure 4: Polygon Area Fill

This task is demonstrated in the following video.

You will now learn about post routing processes.

Next topic: Post Routing Processes