Simulation Library: IBIS Support

What is IBIS?

IBIS (Input/Output Buffer Information Specification) is an EIA/ANSI standard for specifying the input and output behavior of integrated circuits. IBIS models allow you to access up-to-date models for the simulation of your used digital components. Primarily, SI simulation. Currently, IBIS version 3.2 is published as EIA-656-A, and as an American National Standard.

• IBIS Version 4.0 was ratified by the EIA IBIS Open Forum in July 2002.
• IBIS Version 4.1 was ratified by the EIA IBIS Open Forum in January 2003.
• IBIS Version 4.2 was ratified by the EIA IBIS Open Forum in June 2006.
• The IBIS Open Forum ratified version 5.0 of the IBIS format specification in August 2008.
• IBIS Version 5.1 was ratified by the EIA IBIS Open Forum in August 2012.
• IBIS version 6.0 was ratified by the IBIS Open Forum in September 2013.
• IBIS version 6.1 was ratified by the IBIS Open Forum in September 2015.

More IBIS information, including the complete IBIS specification is available on the IBIS home page: https://ibis.org/.

The supported IBIS keywords are listed below.

IBIS Modeling

Switching Characteristics

The switching behavior of the output buffer can be described by v(t) curves for the pull-up and the pull-down tree of push-pull drivers. In IBIS, there are different ways of modeling the switching behavior. The most accurate is the Two-Waveform Approach (TWA), where individual waveforms for the pull-up and pull-down tree describe the switching process, for the rising and falling edge individually. This leads to four switching characteristics. Only two of them are used simultaneously to control the buffers output sources for the single transition. By default, the most advanced data for switching characterization is used. The first complete and valid set of waveforms contained in the IBIS file is used. Otherwise, ramp information is used.

Overclocking

When output buffer models are operated within the SI simulation faster than their switching curve description allows, so called overclocking occurs.

This means that the unit interval in the driver's stimulus definition is shorter than either the rising- or falling waveform.

In some cases this can be caused by an (unnecessary) long initial delay within the model's switching description.

For both, rising and falling waveform, the initial delay is determined automatically during the import process. This initial delay can be used to improve the model's robustness against an overclocking condition. These initial delay values are stored with the model characteristics for use in the SI Analysis.

From IBIS version 6.1 onwards, model makers may describe the initial delay in a specific IBIS keyword: [Initial Delay]. If this value is defined in the IBIS model, it can be used as such in the SI Analysis. No automatically derived values are available in this case.

• By manually defining this parameter in the IBIS file, a user-specified value can be applied.
• By removing this entry, the automatic initial delay procedure is applied.

The presence of an initial delay value in the IBIS model description can be checked in the IBIS file display upon IBIS import.

Model Selector

Devices in IBIS may contain a [Model Selector] statement for different available models per pin. This may be used for specific models for different supply voltage levels or different output driver strength. These models are referenced per pin using a named [Model Selector].

Models are assigned to relevant pins in the same order as they are listed in the model selector. The first named model therefore becomes the active one. Use the Edit function to modify the model order in the IBIS file.

Model Condition

Best case, worst case and typical models are always imported completely. These corner cases can be selected in the Electrical Editor's model selection.

Power Awareness

IBIS models of version 5.0 or newer may contain information about the buffer's behavior considering its connection to the power rails within the package.

Within the component's IBIS file a Pin Mapping table provides the information about the power / ground pin relation of the output buffer models.

This information is considered automatically within the time domain SI Analysis when available.

The impact on the resulting time domain waveforms become significant when multiple buffer models connected to the same package parasitics are switching, simultaneously.

Supported Power Aware IBIS keywords are:

ISSO PU

ISSO PD

Composite Current

Pin Mapping

View the respective characteristics in the Import tool on a selected Power Aware IBIS keyword.

The [Composite Current] characteristics can also be viewed after import within the [Model] view of the Simulation Library Manager.

IBIS Repository within eCADSTAR

On Import, the IBIS and related files are copied into a repository within the eCADSTAR environment. For IBIS V5 files, any AMI model files which it might contain are also copied when an import is completed successfully.

Supported IBIS Keywords

The version of the IBIS Modeling tool is based on the IBIS Golden Parser version 6.1.5 of the IBIS group. However, not all of the possible IBIS Keywords are supported by the Analysis Module. The following tables provide a detailed overview of the IBIS Keywords.

Buffer model keywords are shown below.

Header Section

IBIS Keyword	Supported	Comments
[IBIS Ver]	yes
[Comment Char]	yes	Re-defined anywhere in file
[File Name]	yes
[File Rev]	yes
[Date]	yes
[Source]	yes
[Notes]	yes
[Disclaimer]	yes
[Copyright]	yes

 

Top Level Keywords (with END keywords)

IBIS Keyword	Supported	Comments
[Component]	yes
[Model]	yes
[End]	yes
[Define Package Model]	yes
[End Package Model]	yes
[Model Selector]	yes
[Submodel]	partially	Dynamic clamping is supported in static-mode, only.
[External Circuit]	no
[End External Circuit]	no
[Test Data]	no
[Test Load]	no

 

[Component] Pinout and Package Section

IBIS Keyword	Supported	Comments
[Component]	yes
[Manufacturer]	yes
[Package]	yes
[Pin]	yes
[Pin Mapping]	partially	for output buffers
[Diff Pin]	partially	No related information (vdiff, tdelay).
[Package Model]	partially	Coupled package information is not supported.
[Series Pin Mapping]	partially	[Function_Table_Groups] are not supported.
[Series Switch Groups]	no
[Alternate Package Models]	no
[End Alternate Package Models]	no
[Node Declarations]	no
[End Node Declarations]	no
[Circuit Call]	no
[End Circuit Call]	no
[Begin EMI Component]	no
[End EMI Component]	no
[Repeater Pin]	no

 

[Model] Section

IBIS Keyword	Supported	Comments
[Model]	yes
[Voltage Range]	yes
[Pulldown]	yes
[Pullup]	yes
[GND Clamp]	yes
[POWER Clamp]	yes
[Ramp]	yes
[Temperature Range]	no	Stored only.
[Pullup Reference]	yes
[Pulldown Reference]	yes
[POWER Clamp Reference]	yes
[GND Clamp Reference]	yes
[Rgnd]	yes
[Rpower]	yes
[Rac]	yes
[Cac]	yes
[Rising Waveform]	yes
[Falling Waveform]	yes
[Model Spec]	partially	Stored only.
[Driver Schedule]	yes
[TTgnd]	no	Dynamic clamping effect.
[TTpower]	no	Dynamic clamping effect.
[On]	yes
[Off]	yes
[R Series]	yes
[L Series]	yes
[Rl Series]	yes
[C Series]	yes
[Lc Series]	no
[Rc Series]	no
[Series Current]	yes
[Series MOSFET]	yes
[Add Submodel]	yes
[Receiver Thresholds]	partially	Supported from Revision 20 onwards. Stored already in previous versions.
[External Reference]	no
[Test Data]	no
[Rising Waveform Near]	no
[Falling Waveform Near]	no
[Rising Waveform Far]	no
[Falling Waveform Far]	no
[Diff Rising Waveform Near]	no
[Diff Falling Waveform Near]	no
[Diff Rising Waveform Far]	no
[Diff Falling Waveform Far]	no
[Test Load]	no
[External Model]	no
[End External Model]	no
[Begin EMI Model]	no
[End EMI Model]	no
[Algorithmic Model]	yes	AMI-related parameters are supported.
[End Algorithmic Model]	yes	AMI-related parameters are supported.
[ISSO PU]	yes
[ISSO PD]	yes
[Composite Current]	yes
[C_comp Corner]	yes	If C Comp Corner values are provided, then any other C Comp values are overwritten.
[Initial Delay]	partially	Only for V/t initial delay values.

 

[Submodel] Section

IBIS Keyword	Supported	Comments
[Submodel]	partially	Dynamic clamping is supported in static-mode, only.
[Pulldown]	yes
[Pullup]	yes
[GND Clamp]	yes
[POWER Clamp]	yes
[Ramp]	yes
[Rising Waveform]	yes
[Falling Waveform]	yes
[Submodel Spec]	no
[GND Pulse Table]	no
[POWER Pulse Table]	no
[Initial Delay]	partially	Only for V/t initial delay values.

 

[Model] Subparameters

IBIS Keyword	Supported	Comments
[Polarity]	no
[Enable]	yes	Supported directly in HSPICE output. In the Analysis Module, a positive enable logic is assumed within the stimulus definition.
[Model_type]	yes
[C_comp]	yes
[Vinl]	yes
[Vinh]	yes
[Cref]	yes
[Rref]	yes
[Vref]	yes
[Vmeas]	yes
[C_comp_pullup]	yes
[C_comp_pulldown]	yes
[C_comp_power_clamp]	yes
[C_comp_gnd_clamp]	yes
[Rref_diff]	no
[Cref_diff]	no

 

[Model_Type] Selections

IBIS Keyword	Supported	Comments
[Input]	yes
[Output]	yes
[3-state]	yes
[I/O]	yes
[Open_drain]	yes
[Open_sink]	yes
[Open_source]	yes
[I/O_open_drain]	yes
[I/O_open_sink]	yes
[ I/O_open_source]	yes
[Input_ECL]	yes
[Output_ECL]	yes
[I/O_ECL]	yes
[Terminator]	yes
[3-state_ECL]	yes
[Series]	yes
[Series_switch]	yes
[Input_diff]	no
[Output_diff]	no
3-state_diff]	no
[I/O_diff]	no

 

[Model Spec] Subparameters

IBIS Keyword	Supported	Comments
[Vinh]	yes
[Vinl]	yes
[Vinh+]	no
[Vinh-]	no
[Vinl+]	no
[Vinl-]	no
[S_overshoot_high]	no
[S_overshoot_low]	no
[D_overshoot_high]	no
[D_overshoot_low]	no
[D_overshoot_time]	no
[Pulse_high]	no
[Pulse_low]	no
[Pulse_time]	no
[V_meas]	yes
[Cref]	yes
[Rref]	yes
[Vref]	yes
[Cref_rising]	no
[Cref_falling]	no
[Rref_rising]	no
[Rref_falling]	no
[Vref_rising]	no
[Vref_falling]	no
[Vmeas_rising]	no
[Vmeas_falling]	no
[Rref_diff]	no
[Cref_diff]	no
[Weak_R]	no
[Weak_I]	no
[Weak_V]	no
[D_overshoot_area_h]	no
[D_overshoot_area_l]	no
[D_overshoot_ampl_h]	no
[D_overshoot_ampl_l]	no

 

[Submodel-type] Selections

IBIS Keyword	Supported	Comments
[Dynamic_clamp]	partially	Single dynamic clamp in static mode.
[Bus_hold]	no
[Fall_back]	no

 

[Test_data_type] and [Test_load_type] Selection

IBIS Keyword	Supported	Comments
[Single_ended]	no
[Differential]	no

 

[Begin EMI Component] Keywords

IBIS Keyword	Supported	Comments
[Pin EMI]	no
[Pin Domain EMI]	no

 

[Model_emi_type] Selection

IBIS Keyword	Supported	Comments
[Ferrite]	no
[Not_a_ferrite]	no

 

Subparameters for other Keywords

IBIS Keyword	Subparameter	Supported	Comments
[Submodel]	[Submodel_type]	yes
[Component]	[Si_location]	no
	[Timing_location]	no
[Package]	[R_pkg]	no
	[L_pkg]	no
	[C_pkg]	no
[Pin]	[Signal_name]	yes
	[Model_name]	yes
	[R_pin]	yes
	[L_pin]	yes
	[C_pin]	yes
[Pin Numbers]	[Len]	yes
	[L]	yes
	[C]	yes
	[R]	yes
	[Fork]	yes
	[Endfork]	yes
[Pin List]	[signal_name]	no
[Pin Mapping]	[Pullup Reference]	yes
	[Pulldown Reference]	yes
	[POWER Clamp Reference]	yes
	[GND Clamp Reference]	yes
	[ext_ref]	yes
[Diff Pin]	[inv_pin]	no
	[vdiff]	no
	[t_delay]	no
	[tdelay_min]	no
	[tdelay_max]	no
[Series Pin Mapping]	[Pin_2]	yes
	[Model_name]	yes
	[Function_table_group]	no
[Series Switch Groups]	[On]	no
	[Off]	no
[Series MOSFET]	[Vds]	yes
[Repeater Pin]	tx_non_inv_pin	no
[Initial Delay]	V-T	yes
	I-T	no
[C_Comp Corner]	C_comp	yes
	C_comp_pullup	yes
	C_comp_pulldown	yes
	C_comp_power_clamp	yes
	C_comp_gnd_clamp	yes
[Ramp]	[dv/dt_r]	yes
	[dv/dt_f]	yes
	[R_load]	yes
[Rising Waveform]	[R_fixture]	yes
	[V_fixture]	yes
	[V_fixture_min]	yes
	[V_fixture_max]	yes
	[C_fixture]	no
	[L_fixture]	no
	[R_dut]	yes	Only if only R_fixture is also set.
	[L_dut]	no
	[C_dut]	no
[Falling Waveform]	[R_fixture]	yes
	[V_fixture]	yes
	[V_fixture_min]	yes
	[V_fixture_max]	yes
	[C_fixture]	no
	[L_fixture]	no
	[R_dut]	yes	Only if only R_fixture is also set.
	[L_dut]	no
	[C_dut]	no
[Begin Board Description]	[Len]	no
	[L]	no
	[C]	no
	[R]	no
	[Fork]	no
	[Endfork]	no
	[Node]	no
	[Pin]	no
[Circuit Call]	[Signal_pin]	no
	[Diff_signal_pins]	no
	[Series_pins]	no
	[Port_map]	no
[Receiver Thresholds]	[Vth]	yes
	[Vth_min]	yes
	[Vth_max]	yes
	[Vinh_ac]	yes
	[Vinh_dc]	yes
	[Vinl_ac]	yes
	[Vinl_dc]	yes
	[Threshold_sensitivity]	yes
	[Reference_supply]	yes
	[Vcross_low]	yes
	[V_cross_high]	yes
	[Vdiff_ac]	yes
	[Vdiff_dc]	yes
	[Tslew_ac]	yes
	[Tdiffslew_ac]	yes
[Test Data]	[Test_data_type]	no
	[ Driver_model]	no
	[ Driver_model_inv]	no
[Test Load]	[Test_load_type]	no
	[ C1_near]	no
	[Rs_near]	no
	[Ls_near]	no
	[C2_near]	no
	[Rpl_near]	no
	[Rp2_near]	no
	[Td]	no
	[Zo]	no
	[Rpl_far]	no
	[Rp2_far]	no
	[C1_far]	no
	[Ls_far]	no
	[Rs_far]	no
	[ V_term1]	no
	[V_term2]	no
	[Receiver_model]	no
	[Receiver_model_inv]	no
	[R_diff_near]	no
	[R_diff_far]	no
[External Model]	[Language]	no
	[Corner]	no
	[Parameters]	no
	[Ports]	no
	[D_to_A]	no
	[A_to_D]	no
	[Converter_Parameters]	no
[External Circuit]	[Language]	no
	[Corner]	no
	[Parameters]	no
	[Ports]	no
	[D_to_A]	no
	[A_to_D]	no
	[Converter_Parameters]	no
[Begin EMI Component]	[Domain]	no
	[ Cpd]	no
	[C_Heatsink_gnd]	no
	[C_Heatsink_float]	no
[Pin EMI]	[domain_name]	no
	[clock_div]	no
[Pin Domain EMI]	percentage	no
[Begin EMI Model]	Model_emi_type	no
	Model_Domain	no
[Algorithmic Model]	Executable	yes	Platform_Compiler_Bits File_Name Parameter_File.
	Executable_Rx	yes
	Executable_Tx	yes

 

Package Model Definition (.pkg)

The package model file may contain the following keywords

IBIS Keyword	Supported	Comments
[IBIS Ver]	yes
[Comment Char]	yes	Re-defined anywhere in file
[File Name]	yes
[File Rev]	yes
[Date]	yes
[Source]	yes
[Notes]	yes
[Disclaimer]	yes
[Copyright]	yes
[Define Package Model]	yes
[End Package Model]	yes
[End]	yes
[Manufacturer]	yes
[OEM]	yes
[Description]	yes
[Number Of Pins]	yes
[Pin Numbers]	yes
[Model Data]	partially	Coupling is not supported.
[End Model Data]	yes
[Resistance Matrix]	partially	Coupling is not supported.
[Inductance Matrix]	partially	Coupling is not supported.
[Capacitance Matrix]	partially	Coupling is not supported.
[Row]	no
[Bandwidth]	yes
[Number Of Sections]	yes
[Merged Pins]	no

 

Electrical Board Description (.edb)

Additionally, an Electrical Board Description (EDB) may exist as a separate file with the following keywords:

IBIS Keyword	Supported	Comments
[Begin Board Description]	no
[Manufacturer]	no
[Number Of Pins]	no
[Pin List]	no
[Path Description]	no
[Reference Designator Map]	no
[End Board Description]	no